1. Field of the Invention
The present invention relates to a process for producing a semiconductor strain-sensitive sensor which detects a stress, for example, a semiconductor pressure sensor having a diaphragm.
2. Description of the Related Art
A conventional semiconductor pressure sensor has a first protective layer formed on a diaphragm (displacement portion) which displaces when subjected to pressure, and a second protective layer formed on an electrode, through which an electric signal in accordance with the displacement of the diaphragm is taken out, to protect the electrode.
In the process for producing such a semiconductor pressure sensor, the first and the second protective layers are formed over the whole surface of the semiconductor substrate, and the second protective layer over the region to become the diaphragm (merely referred to as over the diaphragm hereinafter) is removed. Since the second protective layer remaining thereover causes a variation in the offset voltage and degrades the temperature characteristics and the linearity in the detection output, the second protective layer is removed.
However, since the first protective layer is a SiO.sub.2 type layer and the second protective layer is a SiO.sub.2 type layer, a SiN type layer or SiO.sub.2 and SiN type composite layer, the first protective layer is also etched at the time of etching the second protective layer. As a result, there arises a problem that the accuracy of detecting the displacement of the diaphragm is degraded.
The problem as described above will be outlined in accordance with the process for producing a conventional semiconductor pressure sensor.
Firstly, as shown in FIG. 7(a), the first protective layer 4 is formed over the whole surface of the semiconductor substrate 1 on which output resistors 2 and piezo resistors (gauge resistors) 3 have been formed. Wiring 5 is then formed by forming a contact portion by a conventional method, and the second protective layer 6 is deposited over the whole surface, followed by forming a resist pattern 7 having an opening over the diaphragm (FIG. 7(b)). The second protective layer 6 over the diaphragm is subsequently removed by etching as shown in FIG. 7(c).
In the case where the first protective layer 4 is a PSG layer 2,000 .ANG. thick and the second protective layer 6 is a CVD SiO.sub.2 layer 5,000 .ANG. thick, the second protective layer 6 is removed by wet etching with HF, HF-CH.sub.3 COOH, etc. or dry etching with CH.sub.4, SF.sub.6, etc. Since the second protective layer 6 has a uniformity of the layer thickness of .+-.20% over the wafer surface, the etching time becomes just equal to the etching time+the over etching time (which is equal to 20% of the etching time). Since the etching selectivity of the first protective layer 4 to the second protective layer 6 is from 2/1 to 1/2, the first protective layer 4 over the wafer surface is also etched when the second protective layer 6 is etched. As a result, the first protective layer comes to have a thickness of from 0 to 1,500 .ANG., and has a reduced or no function as a protective layer.
Even when the combination of the material of the first protective layer 4 and that of the second protective layer 6 is changed, there still remains the problem that the first protective layer 4 is etched at the time of etching the second protective layer 6 due to the thickness distributions of the protective layers and the lack of etching selectivity of the first protective layer 4 to the second protective layer 6.
As described above, when the first protective layer 4 over the diaphragm is etched at the time of etching the second protective layer 6, the first protective layer 4 may have a reduced function as a protective layer. As a result, there arises a problem that the gauge resistors 3 formed over the diaphragm will have a degraded resistance to the environment.